1. Field of the Invention
The present disclosure relates to memory modules and, more particularly, to a memory module and an impedance calibration method of a semiconductor memory device.
2. Description of the Related Art
Semiconductor integrated circuit (IC) devices such as microcontrollers and memory devices receive and transmit data from/to other semiconductor IC devices through a transmission line. For this reason, most semiconductor IC circuit devices include an off-chip driver (OCD) for outputting signals to an external portion from the semiconductor IC device, and an on-die termination circuit (ODT) for preventing a reflection of signals transmitted to the semiconductor IC device from an external portion. In this case, in order to secure signal integrity, it is required to calibrate impedance characteristics of the off-chip driver or the on-die termination circuit. As systems operate at increasingly higher speeds, the need for calibration is also increased.
Some semiconductor memory devices include a separate ZQ terminal to calibrate impedance characteristics of the off-chip driver or the on-die termination circuit. A reference resistor is connected directly to the ZQ terminal, so that an impedance calibration is performed in proportion to an impedance of the reference resistor.
FIG. 1 is a block diagram illustrating a conventional impedance calibration circuit using a ZQ terminal. The impedance calibration circuit of FIG. 1 includes variable impedance circuits 10, 30 and 70, up-down counters 20 and 60, and comparators 40 and 50. The variable impedance circuits 10, 30 and 70 include a PMOS transistor array or an NMOS transistor array. The two variable impedance circuits 10 and 30 have the same configuration as a pull-up circuit of the off-chip driver or the on-die termination circuit. The variable impedance circuit 70 has the same configuration of a pull-down circuit of the off-chip driver or the on-die termination circuit.
In FIG. 1, “VREF” represents a reference voltage, and “UPcode” and “DNcode” represent an n-bit impedance control code which is used to selectively turn on or off the PMOS transistors and NMOS transistors that constitute the variable impedance circuits 10, 30 and 70, to thereby vary an impedance of the variable impedance circuits 10, 30 and 70. Here, “n” represents the number of PMOS or NMOS transistors. “UPcode” and “DNcode” are also applied to the off-chip driver or the on-die termination circuit of a semiconductor memory device, so that PMOS and NMOS transistors, which constitute a pull-up circuit or a pull-down circuit of the off-chip driver or the on-die termination circuit, are turned on or off identically to the PMOS and NMOS transistors, which constitute the variable impedance circuits 10, 30 and 70.
The functions of the components of FIG. 1 are explained below. The first variable impedance circuit 10 and the second variable impedance circuit 30 vary an internal impedance thereof in response to a first impedance control code UPcode. The first up-down counter 20 converts the first impedance control code UPcode in response to a first counter control signal, which is an output signal of the first comparator 40. The first comparator 40 outputs the first counter control signal according to whether or not a voltage of a ZQ terminal is higher than a reference voltage VREF. The second comparator 50 outputs a second counter control signal according to whether or not a voltage of a node A is higher than a voltage of the ZQ terminal. The second up-down counter 60 converts a second impedance control code DNcode in response to the second counter control signal. The third variable impedance circuit 70 varies an internal impedance thereof in response to the second impedance control code DNcode.
Hereinafter, an impedance calibration method using the ZQ terminal is explained with reference to FIG. 1. The first comparator 40 detects whether or not a voltage of a ZQ terminal is higher than a reference voltage VREF to output a first counter control signal. A level of a reference voltage VREF is previously set to a half level of a power voltage VDD. The first up-down counter 20 converts a first impedance control code UPcode in response to a first counter control signal. That is, if a voltage of the ZQ terminal is higher than a reference voltage VREF, this means that an impedance of the first variable impedance circuit 10 is smaller than an impedance of a reference resistor RQ, and thus the first impedance control code UPcode is converted to increase an impedance of the first variable impedance circuit 10 to be higher than a current value. On the other hand, if a voltage of the ZQ terminal is lower than a reference voltage VREF, this means that an impedance of the first variable impedance circuit 10 is larger than an impedance of a reference resistor RQ, and thus a first impedance control code UPcode is converted to decrease an impedance of the first variable impedance circuit 10 to be smaller than a current value. The first impedance control code UPcode is identically applied to the second variable impedance circuit 30, so that an impedance of the second variable impedance circuit 30 has the same value as that of the first variable impedance circuit 10. Accordingly, an impedance of the variable impedance circuits 10 and 30 has the same value as an impedance of the reference resistor RQ. In addition, a voltage level of a ZQ terminal becomes a reference voltage VREF, i.e., a half level of a power voltage VDD.
The second comparator 50 detects whether or not a voltage of a node A is higher than a voltage of a ZQ terminal to a second counter control signal. The second up-down counter 60 converts a second impedance control code DNcode in response to a second counter control signal. That is, if a voltage of a node A is higher than a voltage of a ZQ terminal, this means that an impedance of the third variable impedance circuit 70 is larger than an impedance of the second variable impedance circuit 30, and thus a second impedance control code DNcode is converted to decrease an impedance of the third variable impedance circuit 70 to be smaller than a current value. If a voltage of a node A is lower than a voltage of a ZQ terminal, this means that an impedance of the third variable impedance circuit 70 is smaller than an impedance of the second variable impedance circuit 30, and thus a second impedance control code DNcode is converted to increase an impedance of the third variable impedance circuit 70 to be larger than a current value. Accordingly, an impedance of the third variable impedance circuit 70 has the same value as an impedance of the second variable impedance circuit 30. That is, the impedance of the variable impedance circuits 10, 30 and 70 becomes equal to an impedance of reference resistor RQ.
The impedance control codes UPcode and DNcode are identically applied to the pull-up circuit or the pull-down circuit of the off-chip driver or the on-die termination circuit, and thus an impedance of the off-chip driver or the on-die termination circuit has the same value as an impedance of the variable impedance circuits 30 and 70, i.e., an impedance of the reference resistor RQ.
The impedance calibration using a ZQ terminal, as described above, has been typically employed in small-sized memory systems. However, a main memory that uses a memory module also requires an impedance calibration to improve the accuracy of an impedance.
FIG. 2 is a block diagram illustrating a memory module using a semiconductor memory device, which calibrates impedance characteristics of an off-chip driver or an on-die termination circuit by using a ZQ terminal. The memory module of FIG. 2 includes a plurality of semiconductor memory devices 90-1 to 90-9 and a plurality of reference resistors RQ. In FIG. 2, “cal” represents a calibration command applied from an external portion.
Functions of the components of the memory module of FIG. 2 are explained below. A plurality of semiconductor memory devices 90-1 to 90-9 perform a read operation or a write operation in response to various control signals that are applied from a memory controller (not shown), and calibrates impedance characteristics of an off-chip driver or an on-die termination circuit according to an impedance value of the reference resistor RQ when a calibration command “cal” is applied. The reference resistors RQ are mounted on the memory module and have one end connected to a ground voltage and the other end connected to a ZQ terminal of the semiconductor memory device. Generally, an impedance value of the reference resistors RQ is six to ten times that of a target impedance of the off-chip driver or the on-die termination circuit. One end of the reference resistor RQ is typically connected to a ground voltage, but can be connected to a power voltage.
However, if the memory module, including the semiconductor memory devices that calibrate an impedance calibration using a ZQ terminal, is configured as shown in FIG. 2, the number of the reference resistors mounted on the memory module is increased, which complicates the wiring and causes inefficiencies in cost and space.